Best Paper Award
The following three papers were selected as candidates for the Best Paper Award.
- 19- "AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation" Akram Ben Ahmed (Keio University), Daichi Fujiki (University of Michigan), Hiroki Matsutani (Keio University), Michihiro Koibuchi (National Institute of Informatics, Tokyo) and Hideharo Amano (Keio University)
- 50- "DAPPER: Data Aware Approximate NoC for GPGPU architectures" Venkata Yaswanth Raparti and Sudeep Pasricha (Colorado State University)
- 68- "FreewayNoC: A DDR NoC with Pipeline Bypassing" Ahsen Ejaz (Chalmers University of Technology), Vassilios Papaefstathiou (Foundation for Research & Technology – Hellas) and Ioannis Sourdis (Chalmers University of Technology)
The Best Paper Award of NOCS 2018 goes to:
"DAPPER: Data Aware Approximate NoC for GPGPU architectures", Venkata Yaswanth Raparti and Sudeep Pasricha (Colorado State University)
Presentation Guidline
- Each accepted regular paper/special session paper/tutorial shall prepare an oral presentation in 25 minutes: 20 minutes for the talk and 5 minutes for Q&A.
- There is no template for oral presentations and authors are free to choose a proper template by themselves.
- In the break before the start of their session, the presenters of papers shall give his or her short bio to the session chair for timely introduction.
- A poster session presentation is 4 minutes with no time for Q&A. Participants may discuss their proposal with other attendees in front of their posters during the coffee break.
Venue
NOCS 2018 is co-located with ESWeek, which will be hosted at the TorinoIncontra Congress Center. The location is in the city center.
Advance Program
| Thursday October 4, 2018 | ||
|---|---|---|
| Time | Activity | Location |
| 9:00-9:10 | Opening Ceremony | Cavour |
| 9:10-10:10 | Keynote I
Session chair: Paul Bogdan (University of Southern California) "Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities" |
Cavour |
| 10:10-10:30 | Posters and Coffee Break | |
| 10:30-12:35 | Regular Paper Session I: Interconnected Multiprocessor
Session chair: Jiang Xu (Hong Kong University of Science and Technology) 64- "NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators" 73- "Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs" 31- "Accurate Congestion Control for RDMA Transfers" 56- "Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects" 17- "Towards Energy-efficient High-throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs" |
Cavour |
| 12:35-14:00 | Lunch | |
| 14:00-16:05 | Regular Paper Session II: Emerging NoC Architecture and Security
Session chair: Luca Carloni (Columbia University) 19 (Best Paper Candidate)- "AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation" 50 (Best Paper Candidate)- "DAPPER: Data Aware Approximate NoC for GPGPU architectures" 68 (Best Paper Candidate)- "FreewayNoC: A DDR NoC with Pipeline Bypassing" 34- "Brownian Bubble Router: Enabling Deadlock Freedom via Guaranteed Forward Progress" 74- "Abetting Planned Obsolescence by Aging 3D Networks-on-Chip" |
Cavour |
| 16:05-16:30 | Posters and Coffee Break | |
| 16:30-17:45 | Special Session I: Securing Networks-on-Chip: A Cross-Technology Perspective
Session chair: Amlan Ganguly (Rochester Institute of Technology) 1- "Securing NoCs against Timing Attacks with Non-Interference Based Adaptive Routing" 2- "Securing Photonic NoC Architectures from Hardware Trojans" 3- "Architecting a Secure Wireless Network-on-Chip" |
Cavour |
| 17:45-18:00 | Poster Session
Session chair: Mario Casu (Politecnico di Torino) 57- "A Learning-Based Thermal-Sensitive Routing for Power Optimization of Optical NoCs" 59- "Approximate Communication for Energy Efficient Networks on Chip" 45- "Improving the Efficiency of Router Bypass" 62- "An Operating System Service for Remote Memory Accesses in Low-Power NoC-Based Manycores" |
Cavour |
| 19:00 ~ | Banquet | Ristorante Circolo dei Lettori |
| Friday October 5, 2018 | ||
| Time | Activity | Location |
| 9:00-10:00 | Keynote II
Session chair: Jiang Xu (Hong Kong University of Science and Technology) "NoCs: a short history of success and a long future" |
Cavour |
| 10:00-10:30 | Posters and Coffee Break | |
| 10:30-11:45 | Regular Paper Session III: Cutting-Edge Network-on-Chip
Session chair: Jie Han (University of Alberta) 21- "A Low-overhead Multicast Bufferless Router with Reconfigurable Banyan Network" 63- "Critical Packet Prioritisation by Slack-Aware Re-routing in On-Chip Networks" 32- "A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multi-Path Channel Environment" |
Cavour |
| 11:45-12:35 | Tutorial: Approximate Computing for Networks on Chip
Session chair: Paul Bogdan (University of Southern California) Part I: "Approximate Arithmetic Circuits" Part II: "Approximate Networks on Chip" |
Cavour |
| 12:35-14:00 | Lunch | |
| 14:00~15:15 | Industrial Session
Session chair: Zhonghai Lu (KTH Royal Institute of Technology) 1- "Challenges and Opportunities for Edge Cloud architectures" 2- "Identifying the gaps between academic research and physical realization of NoCs" 3- "Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus" |
Cavour |
| 15:15-16:05 | Special Session II: Networks Meet Network: Shaping the On-chip Network for Complex Networks
Session chair: Sriram Vangal (Intel) 1- "Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era" 2- "Reconfigurable Network-on-Chip for 3D Neural Network Accelerators" |
Cavour |
| 16:05-16:30 | Posters and Coffee Break | |
| 16:30-17:45 | Special Session III: Realistic Wireless Channel Modelling for Parallel Applications on NoC-based MPSoC
Session chair: Maurizio Palesi (University of Catania) 1- "Accurate Channel Models for Realistic Design Space Exploration of Future Wireless NoCs" 2- "Channel Characterization for Chip-scale Wireless Communications within Computing Packages" 3- "On-Chip Wireless Channel Propagation: Impact of Antenna Directionality and Placement on Channel" |
Cavour |
| 17:45-18:00 | Closing Remark with Best Paper Announcement | Cavour |
Keynote Talks
Keynote 1
Date: October 4th, 2018
Speaker: Vivek De (Intel)
Title: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities
Abstract
Many-core SoC designs in scaled CMOS process demand wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, as well as fine-grain multi-voltage design and spatio-temporal power management to deliver maximum performance under stringent thermal and energy constraints. Interconnect scaling bottlenecks, process-voltage-temperature variations and aging-induced degradation pose major challenges going forward. We present key circuit and design techniques for logic, memory and on-die interconnect networks that enable efficient, variation-tolerant and resilient many-core SoC designs in nanoscale CMOS.
Biography
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 269 publications in refereed international conferences and journals with a citation H-index of 73, and 220 patents issued with 30 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He also co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his publications received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Prolific Contributor to the IEEE International Solid-State Circuits Conference (ISSCC) at its 60th Anniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017 . He served as an IEEE/EDS Distinguished Lecturer in 2011 and an IEEE/SSCS Distinguished Lecturer in 2017-18. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.
Keynote 2
Date: October 5th, 2018
Speaker: Giovanni De Micheli (EPF Lausanne, Switzerland)
Title: NoCs: a short history of success and a long future (Slides)
Abstract
The broad application of NoCs in IC design has been enabled by NoC synthesis tools that evolved from university prototypes to full commercial synthesis flows. NoC embodiments are ubiquitously present in circuits and systems. As systems evolve to include new components and features, NoCs will play even a more important role as the smart connect that can enable heterogeneity.Thus this field will both evolve in diversity of implementations as well in the search of both higher performance and lower power solutions.
Biography
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 750 technical articles. His citation h-index is 93 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.
Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012) and Mobihealth(2016).
He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).
Special Sessions and Tutorial
Special Sessions
- “Securing Networks-on-Chip: A Cross-Technology Perspective”
Organizer: Sudeep Pasricha, Colorado State University
Other Speakers: Tushar Krishna, Georgia Institute of Technology; Travis Boraten, Ohio University
Abstract: This special session will discuss the security challenges in NoC design across the electrical, photonic, and wireless implementation domains, and propose several promising solutions to overcome them. The NOCS community will find the topic of this special session to be extremely relevant and interesting as traditionally the community has not focused on security as much as other design metrics such as performance or energy. Not only will the special session educate and inform attendees about security issues in NoCs across a broad set of implementation technologies, but many of the solutions that will be presented are likely to spark new ideas for NOCS attendees to integrate security into their sub-domain of expertise. This special session will foster a valuable cross-domain exchange of ideas between experts in security, emerging technologies, and NoC design, that is very likely to benefit the industry practitioners and researchers in the NOCS community. - “Realistic Wireless Channel Modelling for Parallel Applications on NoC-based MPSoC”
Organizers/Speakers: Jean-Philippe Diguet, Lab-STICC, France; Sujay Deb, IIIT Delhi, India; Sergi Abadal, Universitat Politècnica de Catalunya, Spain
Abstract: Wireless Network-on-Chip (WNoC) is considered as a promising solution in the context of manycore architectures. Unfortunately, WNoC still suffer from important limitations. The first one is the power consumption of the analog part of the transceivers with is one order of magnitude (tens mW) larger than the power consumption of digital components. Secondly, at network level no feasible simulation is possible today with the existing setup. Apart from transceiver component in WNoC, channel modelling is one of the major concerns. Finally, multiple important radio parameters with strong impacts on communication quality and efficiency are not considered or based on simple and non-meaningful models. The special session addresses this specific but key challenge for future NoC. Research in that area require multidisciplinary teams including NoC experts (architecture, protocols, simulators) and High Frequency radio experts (channel modeling, transceiver design along with digital components, antennas). It will be based on talks and papers from three research groups that investigate this important problem with a multidisciplinary approach. - “Networks Meet Network: Shaping the On-chip Network for Complex Networks”
Organizers: Xiaohang Wang, South China University of Technology; Amit Kumar Singh, University of Essex, UK.
Speakers: Masoud Daneshtalab, Amit Kumar Singh
Abstract: Various emerging applications are in the form of complex networks, e.g., neural networks, deep learning, social networks, protein networks, brain neural connections, and many other applications. A key feature of these applications are "linked", i.e., time varying topologies, complex connection structure, and highly dynamic runtime behaviors. Conventional many-core architecture are inefficient for these "linked" complex network applications, as most of them are using fixed, low-degree mesh network for sustaining on-chip communication, which cannot be adapted to the highly dynamical features of these applications. Therefore, this special session, covers the topic of the interplay of new on-chip networks which can adapt their communication infrastructure to these complex network applications.
Tutorial
- "Approximate Computing for Networks on Chip"
Organizers: Dr. Jie Han (University of Alberta) and Dr. Eun Jung (EJ) Kim (Texas A&M University).- Part I: "Approximate Arithmetic Circuits"
Speaker: Dr. Jie Han
Abstract: The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition and data analytics), have driven the development of approximate computing circuits. Often as the most important arithmetic modules in a processor, adders, multipliers and dividers determine the performance and energy efficiency of many computing tasks. In this talk, a review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers and dividers. A comprehensive and comparative evaluation of their error and circuit characteristics is performed for understanding the features of various designs. Image processing and cerebellar models are considered to show the effectiveness of the approximate arithmetic circuits in improving the energy efficiency and performance of computation-intensive applications.
- Part II: "Approximate Networks on Chip"
Speaker: Dr. Eun Jung (EJ) Kim
Abstract: The trend of unsustainable power consumption and large memory bandwidth demands in massively parallel multicore systems, with the advent of the big data era, has brought upon the onset of alternate computation paradigms utilizing heterogeneity, specialization, processor-in-memory and approximation. Approximate Computing is being touted as a viable solution for high performance computation by relaxing the accuracy constraints of applications. This trend has been accentuated by emerging data intensive applications in domains like image/video processing, machine learning and big data analytics that allow inaccurate outputs within an acceptable variance. Leveraging relaxed accuracy for high throughput in Networks-onChip (NoCs), which have rapidly become the accepted method for connecting a large number of on-chip components, has not yet been explored. In this talk, I will present APPROX-NoC, a hardware data approximation framework with an online data error control mechanism for high performance NoCs. APPROX-NoC facilitates approximate matching of data patterns, within a controllable value range, to compress them thereby reducing the volume of data movement across the chip.
- Part I: "Approximate Arithmetic Circuits"
Industrial Session
- "Challenges and Opportunities for Edge Cloud architectures"
Francesc Guim (Intel Corporation) - "Identifying the gaps between academic research and physical realization of NoCs"
Zhiguo Ge (Huawei International Pte Ltd) - "Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus"
Benoît Dupont de Dinechin (Kalray S.A.)